Design and Implementation of Sequential Logie Circuit Evolution on Chip
[1]LOU Jianan,LI Chuantao,CHANG Xiaolong,et al.Design and Implementation of Sequential Logie Circuit Evolution on Chip[J].Journal of Zhengzhou University (Engineering Science),2012,33(06):10-14.[doi:10.3969/j.issn.1671-6833.2012.06.003]
Copy
Journal of Zhengzhou University (Engineering Science)[ISSN
1671-6833/CN
41-1339/T] Volume:
33卷
Number of periods:
2012 06
Page number:
10-14
Column:
Public date:
2012-11-10
- Title:
- Design and Implementation of Sequential Logie Circuit Evolution on Chip
- Keywords:
- sequential logic; evolution; on chip circuit; Microblaze
- CLC:
- TP 302.1
- DOI:
- 10.3969/j.issn.1671-6833.2012.06.003
- Abstract:
- EHW ( Evolvable Hardware) technique has the advantages of fault tolerant operation, self diagno-sis, adaptive and self repairing, so it has high application value in electronic automation design. Sequentiallogic circuit as a part of evolvable hardware has the problem of multiple states and the fitness function in theimplementation, and is not easy to build, In this paper, based on existing studies and traditional sequentialcireuit design method, we developed sequential logic circuit evalution model, and in the Xilinx FPGA Virtex-5 ( XC5 VL.X110T) established the Microblaze core running GA algorithm for the VRC confguration and evolu-tion. In the same model, by changing the GA program we also designed “1001" detectors, two, four, eightfrequeney divider, So it successfully demonstrated the validity and versatility of the model. The experimentwas in-depth analyzed the evolution performance with random seeds, and provided a reference for the further design.
- References:
- -
- Similar References:
Memo
-
Last Update:
1900-01-01