Digital—based High Speed Serial Link Receiver
[1]LI Haoliang,JIA Heng,LI Changqing,et al.Digital—based High Speed Serial Link Receiver[J].Journal of Zhengzhou University (Engineering Science),2009,30(04):116-119.
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Journal of Zhengzhou University (Engineering Science)[ISSN
1671-6833/CN
41-1339/T] Volume:
30卷
Number of periods:
2009年04期
Page number:
116-119
Column:
Public date:
1900-01-01
- Title:
- Digital—based High Speed Serial Link Receiver
- Keywords:
- high—speed serial link; receiver; high—precision on-chip termination resistor; high—precision on-chip clock generator
- CLC:
- -
- DOI:
- -
- Abstract:
- The receiver is central module in serial link．Involved in digital—based analog circuit-design technology and negative—feedback dynamic adjustment method，this paper brings forward a high speed serial receiver，which consists of sampling—amplifier，clock-generator，matching resistor．The latter two pans determine performance of receiver．Using Cadence’s SPECTRE software and TSMC’S library of 0．25 am mixed—signal CMOS model，simulation resuhs revealed that the clock-generator produces five 480Mbps equal-spaced clock signals between one another．Time interval between each other keeps 0．41 6 ns with jitter of 35 ps，lock time of 1．8 IXS；the value of resistor rangs within[44．3 n，45．6 n]，maximum time leveling off is less than 6 Ixs，average error is±1．45％，maximum error range within 1．56％．Altogether the whole receiver possess capacity in receiving 480 Mbps serial data．
- References:
- -
- Similar References:
Memo
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Last Update:
1900-01-01