A SVPWM Hardware Architecture Based on FPGA and Its Computational Speed Optimization

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A SVPWM Hardware Architecture Based on FPGA and Its Computational Speed Optimization

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[1]LIU Deping,XIN Yunchuan,LIU Zixu.A SVPWM Hardware Architecture Based on FPGA and Its Computational Speed Optimization[J].Journal of Zhengzhou University (Engineering Science),2024,45(03):96-102.[doi:10.13705/j.issn.1671-6833.2023.06.001]

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Journal of Zhengzhou University (Engineering Science)[ISSN 1671-6833/CN 41-1339/T] Volume: 45 Number of periods: 2024 03 Page number: 96-102 Column: Public date: 2024-04-20

Title:: A SVPWM Hardware Architecture Based on FPGA and Its Computational Speed Optimization

Author(s):: LIU Deping; XIN Yunchuan; LIU Zixu; School of Mechanical and Power Engineering, Zhengzhou University, Zhengzhou 450001, China

Keywords:: SVPWM; hardware architecture; inverse Clarke transform; FPGA; optimization of computing speed

CLC:: TM464

DOI:: 10.13705/j.issn.1671-6833.2023.06.001

Abstract:: In order to improve the modulation speed of seven segment two-level SVPWM algorithm and reduce the use of logic resources, a hardware architecture of SVPWM based on FPGA was proposed. After inputting the reference voltage, the hardware architecture first carried out the coordinate transformation based on the inverse Clarke transform, constructed three groups of intermediate variables containing three-phase duty cycle through a series of addition operations, and obtained the simplified 2 bit sector judgment conditions from the above hardware wiring through two XOR operations. Then, according to the simplified 2 bit sector judgment conditions, the three-phase duty cycle was selected from the above three groups of intermediate variables, and clamp protection was carried out, and PWM was output according to the natural sampling method. The above process formed a whole. The whole process from reference voltage input to three-phase PWM output had been completed in two clock cycles with only three triggers in FPGA, which effectively improved the calculation speed. In addition, the resource usage of the hardware architecture with different FPGA platforms was also given. Compared with other methods, the LUT usage was reduced from at least 500 to about 300, and the logical resource usage was reduced. The effectiveness of the proposed hardware architecture was verified by simulation and physical test.

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