An Adaptive Test Method of IC Based on Random Forest

NAVIGATE

Table of Contents

STATISTICS

Viewed2445

Downloads1647

An Adaptive Test Method of IC Based on Random Forest

[HTML] PDF下载 (1647)

[1]Yi Maoxiang,Song Chenyu,Yu Jinxing,et al.An Adaptive Test Method of IC Based on Random Forest[J].Journal of Zhengzhou University (Engineering Science),2021,42(04):13-18.[doi:10.13705/j.issn.1671-6833.2021.02.016]

Copy

Journal of Zhengzhou University (Engineering Science)[ISSN 1671-6833/CN 41-1339/T] Volume: 42卷 Number of periods: 2021 04 Page number: 13-18 Column: Public date: 2021-07-30

Title:: An Adaptive Test Method of IC Based on Random Forest

Author(s):: Yi Maoxiang; Song Chenyu; Yu Jinxing; Song Titan; Lu Yingchun; Huang Zhengfeng;; School of Electronic Science and Application Physics of Hefei University of Technology;

Keywords:: IC test; random forest; adaptive test; test time; test cost

CLC:: -

DOI:: 10.13705/j.issn.1671-6833.2021.02.016

Abstract:: An adaptive test method based on random forest was proposed to solve the problem of high test cost caused by increasing test time.For the chip of the training model,by calculating the Gini index,the importance of each test group to the model classification in the process of the chip parameter test was obtained,and the feature importance was used to quantify it.Then the importance of the test group was ranked to screen out the most important test groups for predicting the quality of the chip.At the same time,the number of defective chips that could be detected in each test group was counted.Part of the test was performed on the chips in the test set,the test time was reduced by deleting some test groups,and the random forest algorithm was used to predict the quality of the chips,so as to achieve a compromise between prediction accuracy and less time.Experimental results showed that compared with KNN and logistic regression algorithms,random forest could always maintains the best prediction accuracy,test escape level and running time.Compared with traditional test methods,the test time could be reduced by about 28% while maintaining a low test escape level.Compared with the other two representative adaptive testing methods,the proposed method performed better in reducing the test time.

References:: [1] YILMAZ E,OZEV S,SINANOGLU O,et al.Adaptive testing:conquering process variations[C]//2012 17th IEEE European Test Symposium (ETS).Piscataway：IEEE,2012:1-6.
[2] STRATIGOPOULOS H G,STREITWIESERC.Adaptive test flow for mixed-signal ICs[C]//2017 IEEE 35th VLSI Test Symposium (VTS).Piscataway：IEEE,2017:1-6.
[3] MARINISSEN E J,SINGH A,GLOTTER D,et al.Adapting to adaptive testing[C]//2010 Design,Automation&Test in Europe Conference &Exhibition (DATE 2010).Piscataway：IEEE,2010:556-561.
[4] CHEN M J,ORAILOGLU A.Test cost minimization through adaptive test development[C]//Proceedings of the IEEE International Conference on Computer Design.Piscataway：IEEE,2008:234-239.
[5] AKKOUCHE N,MIR S,SIMEU E,et al.Analog/RF test ordering in the early stages of production testing[C]//2012 IEEE 30th VLSI Test Symposium (VTS).Piscataway：IEEE,2012:25-30.
[6] XUE C,SHAWN R D.A one-pass test-selection method for maximizing test coverage[C]//2015 33rd IEEE International Conference on Computer Design (ICCD).Piscataway：IEEE,2015:621-628.
[7] GONÇALVES H,LI X,CORREIA M,et al.A fast spatial variation modeling algorithm for efficient test cost reduction of analog/RF circuits[C]//2015 Design,Automation &Test in Europe Conference &Exhibition (DATE).Piscataway：IEEE,2015:1042-1047.
[8] AHMADI A,NAHAR A,ORR B,et al.Wafer-level process variation-driven probe-test flow selection for test cost reduction in analog/RF ICs[C]//2016 IEEE 34th VLSI Test Symposium (VTS).Piscataway：IEEE,2016:1-6.
[9] WANG K L,LIN B Y,WU C W,et al.Test cost reduction methodology for InFO wafer-level chip-scale package[J].IEEE design &test,2017,34(3):50-58.
[10] GRADY M,PEPPER B,PATCH J,et al.Adaptive testing-cost reduction through test pattern sampling[C]//2013 IEEE International Test Conference (ITC).Piscataway：IEEE,2013:1-8.
[11] LIU M Y,PAN R J,YE F M,et al.Fine-grained adaptive testing based on quality prediction[C]//2018 IEEE International Test Conference (ITC).Piscataway：IEEE,2018:1-10.
[12] AGRAWAL M,CHAKRABARTYK.Test-cost modeling and optimal test-flow selection of 3-D-stacked ICs[J].IEEE transactions on computer-aided design of integrated circuits and systems,2015,34(9):1523-1536.
[13] HSU C K,SARSON P,SCHATZBERGER G,et al.Variation and failure characterization through pattern classification of test data from multiple test stages[C]//2016 IEEE International Test Conference (ITC).Piscataway：IEEE,2016:1-10.
[14] AHMADI A,XANTHOPOULOS C,NAHAR A,et al.Harnessing process variations for optimizing wafer-level probe-test flow[C]//2016 IEEE International Test Conference (ITC).Piscataway：IEEE,2016:1-8.
[15] GOTKHINDIKAR K R,DAASCH W R,BUTLER K M,et al.Die-level adaptive test:real-time test reordering and elimination[C]//2011 IEEE International Test Conference.Piscataway：IEEE,2011:1-10.
[16] 李燕燕,杨昊天,曾玙璠.基于随机森林MOPSO的城市最优资本结构分析[J].郑州大学学报(工学版),2019,40(4):80-85.

Similar References:

Memo

Last Update: 2021-08-26