Chaos;  Tangential delay elliptic reflector mapping chaotic system;  Chaotic pseudo-random sequence generator;  Field programmable gate array;  Statistical characteristics

With the development of chaos theory applied to generate pseudo-random sequences, a pseudo-random sequence generator based on TD-ERCS chaos is implemented with field programmable logic gate arrays. In order to facilitate hardware implementation and reduce hardware resources, the original algorithm (that is, the algorithm for constructing pseudo-random sequence generators based on TD-ERCS) was appropriately improved, and the key space was reduced to 2160. The hardware circuit of the system occupies 1 logic cells, accounting for 20% of chip resources, operating at 400 MHz and generating 17716 Mbps in CPRS.