Design of Parallel Multiplier Based on Radix-4 Booth Coding
[1]Fan Wenbing,ZHOU Jianzhang.Design of Parallel Multiplier Based on Radix-4 Booth Coding[J].Journal of Zhengzhou University (Engineering Science),2024,45(pre):2-.[doi:10. 13705 / j. issn. 1671-6833. 2024. 04. 011]
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Journal of Zhengzhou University (Engineering Science)[ISSN
1671-6833/CN
41-1339/T] Volume:
45
Number of periods:
2024 pre
Page number:
2-
Column:
Public date:
2024-12-31
- Title:
- Design of Parallel Multiplier Based on Radix-4 Booth Coding
- Keywords:
- Radix-4 Booth coding; area; transmission delay; encoder; decoder; wallace compression
- CLC:
- TN042
- DOI:
- 10. 13705 / j. issn. 1671-6833. 2024. 04. 011
- Abstract:
- Speed and area are two basic indexes to evaluate the performance of multiplier unit. Aiming at the problem of balancing layout area and transmission delay in current multiplier design, a new 16-bit signed fixed-point multiplier is designed by using Radix-4 Booth algorithm. In the process of partial product generation: firstly, the complementary code circuit for multiplier is improved, and then the modified Booth encoder and decoder with radix 4 are optimized. This structure uses less logic gate resources and is easy to parallelize the input bits. In the Wallace compression circuit: the symbol extension bits are preprocessed and a new compressor structure is designed to optimize the whole Wallace compression module. In the second stage of compression, the ripple carry adder (RCA) structure is used to calculate the high bits in advance, which reduces the sum bits of multi-bit pseudo-sums. In the summation circuit: a two-stage carry look-ahead adder (CLA) structure is used to shorten the transmission delay of the critical path and avoid increasing the chip area, thus improving the running speed of the multiplier. Compared with the existing multiplier structure, the new fixed-point multiplier reduces the area by 12.0% and the delay by 20.5%
- References:
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Last Update:
2024-10-10