Generation of Combinational Circuit Test Suite Combined with Compilation Feature
[1]LI Tianyi,FU Ku,CENG Yuehua,et al.Generation of Combinational Circuit Test Suite Combined with Compilation Feature[J].Journal of Zhengzhou University (Engineering Science),2014,35(02):65-69.[doi:10.3969/j.issn.1671-6833.2014.02.015]
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Journal of Zhengzhou University (Engineering Science)[ISSN
1671-6833/CN
41-1339/T] Volume:
35
Number of periods:
2014 02
Page number:
65-69
Column:
Public date:
2014-04-30
- Title:
- Generation of Combinational Circuit Test Suite Combined with Compilation Feature
- CLC:
- -
- Abstract:
- By researching the generation ol test suite in combinational eireuit testing instrimenis, a generatonof combinational cireuit test suite combined with compilation feature was proposed. The generation of testsuite, which combined the compilers prineiples with test suite generation algorithm, solving some diffieulproblems in combinational cireuit testing instruments ; the type of tested chip is not easy to expand, hardwaredesign cireuit is complexity, and so on. This paper starts from the funetional expression of tested chip, elabo.rating the analysis proeess of the lexieal, syntax and semanties in detail. And taking eritieal path method forexample , this paper gives a detailed design scheme of the test suite generation. Finally, aeeording to the de.sign, we designed a combinational cireuit test system based on STC89C52 chip, and gave the performanee testresults of the system.
- References:
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