[1]Sheng Liyuan,LIU Nian,Cao Liling.FPGA implementation of a chaotic pseudo-random sequence generator[J].Journal of Zhengzhou University (Engineering Science),2008,29(01):44-47.
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Journal of Zhengzhou University (Engineering Science)[ISSN
1671-6833/CN
41-1339/T] Volume:
29卷
Number of periods:
2008年01期
Page number:
44-47
Column:
Public date:
1900-01-01
- Title:
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FPGA implementation of a chaotic pseudo-random sequence generator
- Author(s):
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Sheng Liyuan; LIU Nian; Cao Liling
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- Keywords:
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- CLC:
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- DOI:
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- Abstract:
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With the development of chaos theory applied to generate pseudo-random sequences, a pseudo-random sequence generator based on TD-ERCS chaos is implemented with field programmable logic gate arrays. In order to facilitate hardware implementation and reduce hardware resources, the original algorithm (that is, the algorithm for constructing pseudo-random sequence generators based on TD-ERCS) was appropriately improved, and the key space was reduced to 2160. The hardware circuit of the system occupies 1 logic cells, accounting for 20% of chip resources, operating at 400 MHz and generating 17716 Mbps in CPRS.