[1]刘德平,辛云川,刘子旭.一种基于FPGA 的SVPWM 硬件架构及其计算速度优化[J].郑州大学学报(工学版),2024,45(03):96-102.[doi:10. 13705/ j. issn. 1671-6833. 2023. 06. 001]
 LIU Deping,XIN Yunchuan,LIU Zixu.A SVPWM Hardware Architecture Based on FPGA and Its Computational Speed Optimization[J].Journal of Zhengzhou University (Engineering Science),2024,45(03):96-102.[doi:10. 13705/ j. issn. 1671-6833. 2023. 06. 001]
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一种基于FPGA 的SVPWM 硬件架构及其计算速度优化()
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《郑州大学学报(工学版)》[ISSN:1671-6833/CN:41-1339/T]

卷:
45
期数:
2024年03期
页码:
96-102
栏目:
出版日期:
2024-04-20

文章信息/Info

Title:
A SVPWM Hardware Architecture Based on FPGA and Its Computational Speed Optimization
文章编号:
1671-6833( 2024) 03-0096-07
作者:
刘德平 辛云川 刘子旭
郑州大学 机械与动力工程学院,河南 郑州 450001
Author(s):
LIU Deping XIN Yunchuan LIU Zixu
School of Mechanical and Power Engineering, Zhengzhou University, Zhengzhou 450001, China
关键词:
SVPWM 硬件架构 Clarke 逆变换 FPGA 计算速度优化
Keywords:
SVPWM hardware architecture inverse Clarke transform FPGA optimization of computing speed
分类号:
TM464
DOI:
10. 13705/ j. issn. 1671-6833. 2023. 06. 001
文献标志码:
A
摘要:
为了提高七段式两电平SVPWM 算法的调制速度并减少逻辑资源的使用量,提出了一种基于FPGA 的SVPWM 硬件架构。在该硬件架构输入参考电压后,首先,进行基于Clarke 逆变换的坐标变换,通过一系列加法运算构建出含有三相占空比的3 组中间变量,同时通过2 个异或运算从上述硬件布线中得到简化后的2 bit 扇区判断条件;然后,根据简化后的2 bit 扇区判断条件从以上3 组中间变量中筛选出三相占空比,并进行钳位保护,按照自然采样法输出PWM。以上过程形成一个整体,在FPGA 中只需3 次触发,便能在2 个时钟周期内完成从参考电压输入到三相PWM 输出的整个过程,有效提高了计算速度。此外,还给出了该硬件架构在不同的FPGA 平台下的资源使用情况,与其他方法相比,LUT 使用量由至少500 个缩减至300 个左右,逻辑资源使用量降低。通过仿真与实物试验,验证了所提硬件架构的有效性。
Abstract:
In order to improve the modulation speed of seven segment two-level SVPWM algorithm and reduce the use of logic resources, a hardware architecture of SVPWM based on FPGA was proposed. After inputting the reference voltage, the hardware architecture first carried out the coordinate transformation based on the inverse Clarke transform, constructed three groups of intermediate variables containing three-phase duty cycle through a series of addition operations, and obtained the simplified 2 bit sector judgment conditions from the above hardware wiring through two XOR operations. Then, according to the simplified 2 bit sector judgment conditions, the three-phase duty cycle was selected from the above three groups of intermediate variables, and clamp protection was carried out, and PWM was output according to the natural sampling method. The above process formed a whole. The whole process from reference voltage input to three-phase PWM output had been completed in two clock cycles with only three triggers in FPGA, which effectively improved the calculation speed. In addition, the resource usage of the hardware architecture with different FPGA platforms was also given. Compared with other methods, the LUT usage was reduced from at least 500 to about 300, and the logical resource usage was reduced. The effectiveness of the proposed hardware architecture was verified by simulation and physical test.

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备注/Memo

备注/Memo:
收稿日期:2023-05-16;修订日期:2023-06-16
基金项目:河南省重大科技专项资助项目(171100210300-01)
作者简介:刘德平(1966— ),男,河南商丘人,郑州大学教授,博士,主要从事先进制造技术方面的研究,E-mail:ldp@ zzu.edu. cn。
更新日期/Last Update: 2024-04-29