[1]盛利元,刘念,曹莉凌..一种混沌伪随机序列发生器的FPGA实现[J].郑州大学学报(工学版),2008,29(01):44-47.
　Sheng Liyuan,LIU Nian,Cao Liling.FPGA implementation of a chaotic pseudo-random sequence generator[J].Journal of Zhengzhou University (Engineering Science),2008,29(01):44-47.

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一种混沌伪随机序列发生器的FPGA实现()

分享到：

《郑州大学学报(工学版)》[ISSN:1671-6833/CN:41-1339/T]

卷:

29卷

期数:

2008年01期

页码:

44-47

栏目:

出版日期:

1900-01-01

文章信息/Info

Title:

FPGA implementation of a chaotic pseudo-random sequence generator

作者:

盛利元; 刘念; 曹莉凌.

中南大学,物理科学与技术学院,湖南,长沙,410083, 上海水产大学,工程学院,上海,200090

Author(s):

Sheng Liyuan; LIU Nian; Cao Liling

关键词:

混沌;  切延迟椭圆反射腔映射混沌系统;  混沌伪随机序列发生器;  现场可编程门阵列;  统计特性

Keywords:

Chaos;  Tangential delay elliptic reflector mapping chaotic system;  Chaotic pseudo-random sequence generator;  Field programmable gate array;  Statistical characteristics

文献标志码:

A

摘要:

随着混沌理论应用于产生伪随机序列的发展,用现场可编程逻辑门阵列实现了基于TD-ERCS混沌的伪随机序列发生器.为了便于硬件实现并减少硬件占用资源,对原算法(即基于TD-ERCS构造伪随机序列发生器的算法)进行了适当改进,密钥空间缩减到2160.设计采用双精度浮点运算,选用Cyclone系列的EP1C20F400芯片,完成了CPRSG的系统仿真实验.系统的硬件电路占用17716个逻辑单元,占芯片资源88%,工作频率50 MHz,CPRS产生速率10 Mbps.

Abstract:

With the development of chaos theory applied to generate pseudo-random sequences, a pseudo-random sequence generator based on TD-ERCS chaos is implemented with field programmable logic gate arrays. In order to facilitate hardware implementation and reduce hardware resources, the original algorithm (that is, the algorithm for constructing pseudo-random sequence generators based on TD-ERCS) was appropriately improved, and the key space was reduced to 2160. The hardware circuit of the system occupies 1 logic cells, accounting for 20% of chip resources, operating at 400 MHz and generating 17716 Mbps in CPRS.

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