[1]娄建安,李川涛,常小龙,等.时序逻辑电路在片进化设计与实现[J].郑州大学学报(工学版),2012,33(06):10-14.[doi:10.3969/j.issn.1671-6833.2012.06.003]
 LOU Jianan,LI Chuantao,CHANG Xiaolong,et al.Design and Implementation of Sequential Logie Circuit Evolution on Chip[J].Journal of Zhengzhou University (Engineering Science),2012,33(06):10-14.[doi:10.3969/j.issn.1671-6833.2012.06.003]
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时序逻辑电路在片进化设计与实现()
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《郑州大学学报(工学版)》[ISSN:1671-6833/CN:41-1339/T]

卷:
33卷
期数:
2012年06期
页码:
10-14
栏目:
出版日期:
2012-11-10

文章信息/Info

Title:
Design and Implementation of Sequential Logie Circuit Evolution on Chip
作者:
娄建安李川涛常小龙等.
军械工程学院 电气工程系,河北石家庄,050003, 军械工程学院静电与电磁防护研究所,河北石家庄,050003
Author(s):
LOU JiananLI ChuantaoCHANG Xiaolongetc;
1. Department of Electrical Engineering, Ordnance Engineering College, Shijiazhuang 050003, China; 2. institute of Electrostatic and Electromagnetie Protection, Ordnance Engineering College, Shiiazhuang 050003 ,China
关键词:
时序逻辑 演化 在片电路 Microblaze
Keywords:
sequential logic evolution on chip circuit Microblaze
分类号:
TP 302.1
DOI:
10.3969/j.issn.1671-6833.2012.06.003
摘要:
针对EHW(Evolvable Hardware)技术在电子设计自动化、容错运行、自诊断、自适应和自修复等方面的特点,借鉴传统时序电路设计的方法,建立了适应于片内进化的时序电路演化模型和基于Xilinx FPGA Virtex-5 (XC5VLX110T)的Microblaze软核结构,并运行GA算法对本文设计的VRC进行配置、演化.进而,利用设计的时序电路演化模型成功演化了1001检波器以及二、四、八分频器等时序逻辑电路,验证了本模型的有效性、通用性,并深入分析了演化算法中的随机数种子对演化性能的影响,可为演化算法设计提供一定的参考.
Abstract:
EHW ( Evolvable Hardware) technique has the advantages of fault tolerant operation, self diagno-sis, adaptive and self repairing, so it has high application value in electronic automation design. Sequentiallogic circuit as a part of evolvable hardware has the problem of multiple states and the fitness function in theimplementation, and is not easy to build, In this paper, based on existing studies and traditional sequentialcireuit design method, we developed sequential logic circuit evalution model, and in the Xilinx FPGA Virtex-5 ( XC5 VL.X110T) established the Microblaze core running GA algorithm for the VRC confguration and evolu-tion. In the same model, by changing the GA program we also designed “1001" detectors, two, four, eightfrequeney divider, So it successfully demonstrated the validity and versatility of the model. The experimentwas in-depth analyzed the evolution performance with random seeds, and provided a reference for the further design.
更新日期/Last Update: 1900-01-01