[1]李浩亮,贾恒,李常青,等.基于数字化技术的高速串行接收器设计[J].郑州大学学报(工学版),2009,30(04):116-119.
　LI Haoliang,JIA Heng,LI Changqing,et al.Digital—based High Speed Serial Link Receiver[J].Journal of Zhengzhou University (Engineering Science),2009,30(04):116-119.
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基于数字化技术的高速串行接收器设计()
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《郑州大学学报(工学版)》[ISSN:1671-6833/CN:41-1339/T]

卷:
30
期数:
2009年04期
页码:
116-119
栏目:
出版日期:
1900-01-01

文章信息/Info

Title:
Digital—based High Speed Serial Link Receiver
作者:
李浩亮; 贾恒; 李常青; 等.
郑州大学信息工程学院,河南郑州,450001, 郑州大学信息工程学院,河南郑州,450001, 郑州大学信息工程学院,河南郑州,450001, 郑州大学信息工程学院,河南郑州,450001
Author(s):
LI Haoliang; JIA Heng; LI Changqing; etc;
School of Information Engineering，ZhengZhou University，Zhengzhou 450001，China
关键词:
高速串行接口;  接收器;  高精度片上匹配电阻;  时钟发生电路
Keywords:
high—speed serial link; receiver; high—precision on-chip termination resistor; high—precision on-chip clock generator
摘要:
基于数字化模拟电路设计技术和自适应动态反馈方法设计了一个高速串行接收器,包含采样放大器、时钟发生电路、匹配电阻电路.后两者的精度直接决定了接收器性能.采用TSMC的CMOS 0.25μm混合信号模型,在Cadence软件环境下用spectre仿真器进行模拟.结果表明,时钟发生电路输出的五相时钟间隔0.416 ns,抖动35 ps,锁定时间1.8 μs;匹配电阻阻值波动在44.3～45.6 Ω,稳定时间6μs,平均误差±1.45%,最大误差1.56%.联调后整个接收器电路具有接收480 Mbps高速串行数据
Abstract:
The receiver is central module in serial link．Involved in digital—based analog circuit-design technology and negative—feedback dynamic adjustment method，this paper brings forward a high speed serial receiver，which consists of sampling—amplifier，clock-generator，matching resistor．The latter two pans determine performance of receiver．Using Cadence’s SPECTRE software and TSMC’S library of 0．25 am mixed—signal CMOS model，simulation resuhs revealed that the clock-generator produces five 480Mbps equal-spaced clock signals between one another．Time interval between each other keeps 0．41 6 ns with jitter of 35 ps，lock time of 1．8 IXS；the value of resistor rangs within[44．3 n，45．6 n]，maximum time leveling off is less than 6 Ixs，average error is±1．45％，maximum error range within 1．56％．Altogether the whole receiver possess capacity in receiving 480 Mbps serial data．

相似文献/References:

[1]李浩亮,李常青,邓记才,等.一种新颖的高精度片上匹配电阻电路设计[J].郑州大学学报(工学版),2008,29(03):27.[doi:10.3969/j.issn.1671-6833.2008.03.007]
　Li Haoliang,LI Changqing,Deng Jicai,et al.A novel design of high-precision on-chip matching resistor circuit[J].Journal of Zhengzhou University (Engineering Science),2008,29(04):27.[doi:10.3969/j.issn.1671-6833.2008.03.007]
[2]李浩亮,叶会英,徐力平..一种用于高速串行接口电路的偏置产生方法及实现[J].郑州大学学报(工学版),2007,28(02):68.[doi:10.3969/j.issn.1671-6833.2007.02.018]

更新日期/Last Update: 1900-01-01