[1]范文兵,周健章.基于 Radix-4 Booth 编码的并行乘法器设计[J].郑州大学学报(工学版),2024,45(pre):2.[doi:10. 13705 / j. issn. 1671-6833. 2024. 04. 011]
　Fan Wenbing,ZHOU Jianzhang.Design of Parallel Multiplier Based on Radix-4 Booth Coding[J].Journal of Zhengzhou University (Engineering Science),2024,45(pre):2.[doi:10. 13705 / j. issn. 1671-6833. 2024. 04. 011]
点击复制

基于 Radix-4 Booth 编码的并行乘法器设计()
分享到：

《郑州大学学报(工学版)》[ISSN:1671-6833/CN:41-1339/T]

卷:
45
期数:
2024年pre
页码:
2
栏目:
出版日期:
2024-12-31

文章信息/Info

Title:
Design of Parallel Multiplier Based on Radix-4 Booth Coding
作者:
范文兵; 周健章
(郑州大学 电气与信息工程学院,河南 郑州450001)
Author(s):
Fan Wenbing ;  ZHOU Jianzhang
(School of Electrical and Information EngineeringZhengzhou UniversityZhengzhou 450001HenanChina)
关键词:
Radix-4 Booth编码; 面积; 传输延时; 编码器; 解码器; 华莱士压缩
Keywords:
Radix-4 Booth coding; area; transmission delay; encoder; decoder; wallace compression
分类号:
TN042
DOI:
10. 13705 / j. issn. 1671-6833. 2024. 04. 011
文献标志码:
A
摘要:
速度和面积是评价乘法器单元性能优劣的两个基本指标。针对当前乘法器设计难以平衡版图面积和传输延时的问题，采用Radix-4 Booth算法，设计了一种新型的16位有符号定点乘法器。在部分积生成过程中：首先改进对乘数的取补码电路，然后优化基数为4的改进Booth编码器和解码器，此结构采用较少的逻辑门资源，并且易对输入比特进行并行化处理。在华莱士(Wallace)压缩电路中：对符号扩展位进行预处理并设计新的压缩器结构，优化整个Wallace压缩模块。在第二级压缩过程中提前对高位使用纹波进位加法器(Ripple Carry Adder，RCA)结构计算，减小了多bit伪和的求和位数。在求和电路中：使用两级超前进位加法器(Carry Look-ahead Adder，CLA)结构，在缩短关键路径的传输延时的同时避免增大芯片面积，提高了乘法器的运行速度。新型定点乘法器与已有的乘法器结构相比，减少了12.0%的面积，降低了20.5%的延时。
Abstract:
Speed and area are two basic indexes to evaluate the performance of multiplier unit. Aiming at the problem of balancing layout area and transmission delay in current multiplier design, a new 16-bit signed fixed-point multiplier is designed by using Radix-4 Booth algorithm. In the process of partial product generation: firstly, the complementary code circuit for multiplier is improved, and then the modified Booth encoder and decoder with radix 4 are optimized. This structure uses less logic gate resources and is easy to parallelize the input bits. In the Wallace compression circuit: the symbol extension bits are preprocessed and a new compressor structure is designed to optimize the whole Wallace compression module. In the second stage of compression, the ripple carry adder (RCA) structure is used to calculate the high bits in advance, which reduces the sum bits of multi-bit pseudo-sums. In the summation circuit: a two-stage carry look-ahead adder (CLA) structure is used to shorten the transmission delay of the critical path and avoid increasing the chip area, thus improving the running speed of the multiplier. Compared with the existing multiplier structure, the new fixed-point multiplier reduces the area by 12.0% and the delay by 20.5%

参考文献/References:

[1].SIMONYAN K, ZISSERMAN A. Very deep convolutional networks for large-scale image recognition [J]. arXiv preprint arxiv: 1409.1556, 2015.
[2].BU B C, et al. Design of reversible logic based 32-bit MAC unit using radix-16 booth encoded wallace tree multiplier[C]// 2018 International Conference on Computer Communication and Informatics . Coimbatore : IEEE, 2018, 1-6.
[3].HARI S P, et al. An efficient and enhanced memory based FFT processor using radix 16 booth with carry skip adder[C]// 2016 International Conference on Signal Processing, Communication, Power and Embedded System . Paralakhemundi: IEEE, 2016, 1608-1612 .
[4].姚若河,徐新才.基于冗余符号数的定点乘法器的设计[J].华南理工大学学报(自然科学版),2014,42(03):27-34.

Yao R H, Xu X C . Design of fixed-point multiplier based on redundant symbol number [J]. Journal of South China University of Technology (Natural Science), 2014, 42 (03): 27-34.
[5].Scheunemann J C, Sigales M S , Fonseca M B , et al. Optimizing encoder and decoder blocks for a power-efficient radix-4 modified booth multiplier[C]// Proceedings of 2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design. Campinas: IEEE, 2021: 1-6 .
[6].Jain R , Pahwa K, Pandey N, et al. Booth-Encoded karatsuba: a novel hardware-Efficient multiplier[J]. Advances in E lectrical and E lectronic E ngineering, 2021, 19(3): 272–281.
[7].Moni D J, Sophia P E. Design of low power and high speed configurable booth multiplier [C]// Proceedings of 2011 3rd International Conference on Electronics Computer Technology. Kanyakumari : IEEE, 2011: 338-342 .
[8].曾宪恺. 高性能并行乘法器半定制设计方法研究[D].杭州:浙江大学,2012.
Zeng X K. Research on semi custom design method of high-performance parallel multiplier [D]. Hangzhou: Zhejiang University, 2012 .
[9].Patil P A, Kulkarni C. Multiply accumulate unit using radix-4 booth encoding[C]//2018 Second International Conference on Intelligent Computing and Control Systems. Madurai : IEEE, 2018: 1076-1080 .
[10].Ravula M R , Potharaju A, Vidyadhar R P , et al. Designing carry look ahead adder to enrich performance using one bit hybrid full adder[C]// Proceedings of 2022 International Conference on Electronics and Renewable Systems. Tuticorin: IEEE, 2022: 86-89 .
[11].Ram G C , Subbarao M V , Varma D R , et al. Delay enhancement of wallace tree multiplier with binary to excess-1 converter[C]// Proceedings of 2023 5th International Conference on Smart Systems and Inventive Technology. Tirunelveli :IEEE, 2023: 113-117 .
[12].SA S K. Design and performance analysis of multipliers using kogge stone adder [C]// Proceedings of 2017 3rd International Conference on Applied and Theoretical Computing and Communication Technology . Tumkur : IEEE,2017:94-99.

备注/Memo

备注/Memo:
基金项目：河南省科技攻关项目(192102210086) 收稿日期：XXXX-XX-XX
作者简介：范文兵（1969-），男，河南周口人，郑州大学教授，博士，主要从事混合集成电路分析与设计、图像处理与射频识别技术。E-mail: iewbfan@zzu.edu.c n
更新日期/Last Update: 2024-10-10