[1]范文兵,周健章.基于 Radix-4 Booth编码的并行乘法器设计[J].郑州大学学报(工学版),2025,46(01):26-33.[doi:10.13705/j.issn.1671-6833.2024.04.011]
　FAN Wenbing,ZHOU Jianzhang.Design of Parallel Multiplier Based on Radix-4 Booth Coding[J].Journal of Zhengzhou University (Engineering Science),2025,46(01):26-33.[doi:10.13705/j.issn.1671-6833.2024.04.011]
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基于 Radix-4 Booth编码的并行乘法器设计()
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《郑州大学学报(工学版)》[ISSN:1671-6833/CN:41-1339/T]

卷:
46
期数:
2025年01期
页码:
26-33
栏目:
出版日期:
2024-12-23

文章信息/Info

Title:
Design of Parallel Multiplier Based on Radix-4 Booth Coding
文章编号:
1671-6833(2025)01-0026-08
作者:
范文兵;  周健章
郑州大学 电气与信息工程学院,河南 郑州 450001
Author(s):
FAN Wenbing;  ZHOU Jianzhang
School of Electrical and Information Engineering, Zhengzhou University, Zhengzhou 450001, China
关键词:
Radix-4 Booth编码;  面积;  传输延时;  编码器;  解码器;  Wallace压缩
Keywords:
Radix-4 Booth coding;  area;  transmission delay;  encoder;  decoder;  Wallace compression
分类号:
TN402
DOI:
10.13705/j.issn.1671-6833.2024.04.011
文献标志码:
A
摘要:
速度和面积是评价乘法器单元性能优劣的两个基本指标。针对当前乘法器设计难以平衡版图面积和传输延时的问题,采用Radix-4 Booth算法,设计了一种新型的16位有符号定点乘法器。在部分积生成过程中,首先改进对乘数的取补码电路,然后优化基数为4的改进Booth编码器和解码器,此结构采用较少的逻辑门资源,并且易对输入比特进行并行化处理。在Wallace压缩电路中,对符号扩展位进行预处理并设计新的压缩器结构,优化整个Wallace压缩模块。在第二级压缩过程中提前对高位使用纹波进位加法器结构计算,减小了多bit伪和的求和位数。在求和电路中,使用两级超前进位加法器结构,在缩短关键路径传输延时的同时避免增大芯片面积,提高了乘法器的运行速度。新型定点乘法器与已有的乘法器结构相比,减少了12.0%的面积,降低了20.5%的延时。
Abstract:
Speed and area are two basic indexes to evaluate the performance of multiplier unit. Aiming at the problem of balancing layout area and transmission delay in current multiplier design, a new 16-bit signed fixed-point multiplier was designed by using Radix-4 Booth algorithm. In the process of partial product generation, firstly, the complementary code circuit for multiplier was improved, and then the modified Booth encoder and decoder with Radix-4 were optimized. The structure used less logic gate resources and was easy to parallelize the input bits. In the Wallace compression circuit, the symbol extension bits were preprocessed and a new compressor structure was designed to optimize the whole Wallace compression module. In the second stage of compression, the ripple carry adder structure was used to calculate the high bits in advance, which reduced the sum bits of multi-bit pseudo-sums. In the summation circuit, a two-stage carry look-ahead adder structure was used to shorten the transmission delay of the critical path and avoid increasing the chip area, thus improved the running speed of the multiplier. Compared with the existing multiplier structure, the new fixed-point multiplier reduced the area by 12.0% and the delay by 20.5%.

参考文献/References:

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更新日期/Last Update: 2024-12-30