[1]刘雄飞,马剑钊,盛利元..基于改进的分布式结构的二维DCT硬件实现[J].郑州大学学报(工学版),2008,29(01):48-51.
　LIU Xiongfei,Ma Jianzhao,Sheng Liyuan.2D DCT hardware implementation based on improved distributed structure[J].Journal of Zhengzhou University (Engineering Science),2008,29(01):48-51.
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基于改进的分布式结构的二维DCT硬件实现()
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《郑州大学学报(工学版)》[ISSN:1671-6833/CN:41-1339/T]

卷:
29
期数:
2008年01期
页码:
48-51
栏目:
出版日期:
1900-01-01

文章信息/Info

Title:
2D DCT hardware implementation based on improved distributed structure
作者:
刘雄飞; 马剑钊; 盛利元.
中南大学,物理科学与技术学院,湖南,长沙,410083, 中南大学,物理科学与技术学院,湖南,长沙,410083, 中南大学,物理科学与技术学院,湖南,长沙,410083
Author(s):
LIU Xiongfei; Ma Jianzhao; Sheng Liyuan
关键词:
现场可编程门阵列;  离散余弦变换;  联合图像专家组;  分布式算法
Keywords:
文献标志码:
A
摘要:
设计了一个适合JPEG图像压缩系统的二维离散余弦变换模块,采用行列分离的方法,首先设计了一维余弦离散变换单元,该单元采用作者提出的改进的有符号分布式算法结构实现,在硬件实现上可以明显提高吞吐率.然后复用该单元完成二维离散余弦变换的FPGA设计.在所选器件EPF10K100EQC208-1综合后显示,一维余弦离散变换单元的最高频率可达到104.17 MHz,满足JPEG图像压缩系统的高吞吐率要求.
Abstract:
A two-dimensional discrete cosine transformation module suitable for JPEG image compression system is designed, and a one-dimensional cosine discrete transformation unit is first designed by using the method of row-column separation, which adopts the improved symbolic distributed algorithm structure proposed by the author, which can significantly improve the throughput rate in hardware implementation. Then, the unit is multiplexed to complete the FPGA design of two-dimensional discrete cosine transform. After the EPF10K100EQC208-1 of the selected device is synthesized, it is shown that the maximum frequency of the one-dimensional cosine discrete conversion unit can reach 104.17 MHz, which meets the high throughput requirements of JPEG image compression system.

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更新日期/Last Update: 1900-01-01